The present invention relates, in general, to bipolar logic circuits and, more particularly, to an emitter-coupled logic (ECL) gate having an output with active pull-up and low-voltage active pull-down circuitry for use in conjunction with bipolar logic circuits in macrocell-based application specific integrated circuits (ASIC).
Historically, one of the most important advantages to bipolar emitter-coupled logic has been switching speed. In most bipolar logic families, the transistors are operated between a non-conductive state and a highly conductive state in or near the saturation region. It takes a finite amount of time to switch a transistor from off to on. Once the transistor is on, it takes a finite amount of time to turn it off by dissipating the charge that builds up in the base of the device. Additionally, in other logic forms, the total voltage swing is relatively large, thus increasing the delay between input and output transitions. In a complex logic function, these time delays can become significant. With ECL, the transistors in the circuit are operated in the active region, reducing the delays associated with turning on or turning off a device. Furthermore, the total voltage swing is relatively small, thus improving switching speed.
The penalty paid with high speed ECL is that of increased power dissipation. In traditional ECL, the output device was an emitter follower transistor acting as a pull-up device for the output load. The pull-down function was performed by a resistor. The resistor had to be of small enough value so that it could discharge the capacitance associated with the output load with reasonable speed. In a quiescent state, whether the output was high or low, the pull down resistor continued to sink current, which was sourced by the pull-up device. The total quiescent power dissipation of this emitter follower output section was then the sum of the power dissipated in the pull up device due to the quiescent current and the power dissipated in the pull down resistor. This power dissipation component contributed significantly to the total power dissipation of the ECL circuit.
An improved ECL implementation used a current source as a pull-down. This had the advantage of having a linear decay characteristic, rather than the characteristic exponential decay of the RC network, thus making switching speed less sensitive to voltage variations. However, the current source still had to be a relatively large value in order to maintain the desired switching speed. Thus, the problem of high power dissipation still remained.
Another approach used a technique to temporarily turn on an active pull-down device. During switching, the current sinking capability of the output was enhanced, increasing switching speed. During steady state conditions, the circuit was off, reducing power dissipation. This scheme was primarily based upon deriving a "boost" signal from the output of the input differential amplifier. The input differential amplifier normally had two outputs, one the inverse of the other. One was used to drive the output stage of the logic gate. The other was capacitively coupled to the pull-down device, giving it a transient increase in base drive during the time the output logic was being switched to a lower voltage level. There were some disadvantages to this approach. First, the two outputs of the input stage would not necessarily have matching switching characteristics. Further, the switching characteristics of the outputs of the input stage could vary from one logic function to another. The effect was an inconsistency in the results of the active pull-down function. Another disadvantage was that, in macrocell-based ASIC circuits, the complex structure of the macro logic function often made the complementary outputs of the input differential amplifier difficult and costly to realize.